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Debugging incurs significant costs in the semiconductor industry, with some engineers spending 40% or more of their time debugging. Despite the critical importance of this skill, undergraduate students often need help to develop it. In this paper, we administered a circuit debugging test to second and third-year electrical and computer engineering (ECE) students in an introductory microelectronics class. The buggy circuit was a non-inverting amplifier printed circuit board with a misoriented op-amp. The pilot results on 26 students revealed concerns about misconceptions and biases in their debugging methodology. 54% of students focused predominantly on scrutinizing resistors, neglecting a broader exploration of potential issues. Furthermore, 46% limited their search for errors to a single potential problem, and 15% could not accurately measure resistance. Ultimately, 31% successfully identified and corrected the bug, indicating exam expectations were achievable and giving us hope that debugging skills are within reach for our students. However, specialized training may be needed to get them there. 

In the rapidly evolving world of hardware security, developing metrics for evaluating the security improvements of hardware designs is important. This work examines the prevailing threat model for secure analog-to-digital converter (ADC) architectures and explains how signal-to-noise ratio (SNR), root-mean-square error (RMSE), and bit-wise accuracy (BWA) are used to evaluate security improvements. The existing metrics are mathematically related through the proposed Proxy ADC framework. The proposed SNR-RMSE and BWA-RMSE relationships are validated using a power side-channel attack on a commercial ADC. The SNR-RMSE relationship achieves an average percent error of 1.69% across four trials, while the BWA-RMSE relationship achieves an average of 7.97%. Using results from past secure ADC works allows for additional demonstrations of the relationships. These relationships can estimate accuracy in a realistic attack scenario where ADC outputs cannot be measured to verify the evaluation, and recontextualize the metrics of standard ADC design for hardware security. Furthermore, the Proxy ADC framework allows for comparison of tradeoffs between designs’ security and efficiency, revealing trends to leverage for future secure architectures. 

This brief summarizes the first two years of participants’ data from a National Science Foundation (NSF) Research Experiences for Teachers (RET) project on Chip Design (Chip-RET). Semiconductor workforce development has become a national priority due to microchips’ importance to our supply chain security, national defense, and technological leadership. K-14 teachers play a pivotal role in exciting, motivating, and preparing students to join various microelectronics-related career pathways. To meet such requirements, K-14 STEM teachers need to receive the necessary training on the subject matter. Our institution proposed the Chip-RET, the first RET program in the US that focused exclusively on integrated circuit design and K-14 semiconductor education. To evaluate the effectiveness of such training, we further developed a custom semiconductor knowledge and literacy test (SKLT), whose content and interpretation have been validated by semiconductor industry experts. Our data reveals that the Year One cohort of ten teachers demonstrated an increase in their mean percentage of correct responses to the SKLT test, from 39% to 65% pre- and post-RET. A follow-up Wilcoxon Rank-Sum Test underscored the significance of this difference, with a W-value of 3 and a p-value less than 0.001. Moreover, a repeat measure of the SKLT test nine months after the Chip-RET training (post-9 months) showed a mean percentage of correct response of 55%, suggesting that participants were able to retain much of their knowledge gained nearly one year after the training. A Wilcoxon Rank-Sum Test from pre- to post-9 months showed a W-value of 12 and a p-value of 0.007, further confirming the gain despite some loss of knowledge over the nine-month period. Finally, the Year Two cohort of another ten teachers also showed an increase from 48% to 69% pre- and post-RET. The post-9-month data is not yet available and will be collected. 

This work-in-progress research-to-practice paper presents the development and pilot implementation of curriculum that introduces semiconductor contents in a high school calculus class. The demand for chips soared through the COVID-19 pandemic, exposing our country's semiconductor manufacturing and supply chain risks. The need to reassert US semiconductor leadership will require training a well-educated workforce, starting at the K-12 level. Meanwhile, K-12 STEM teachers often juggle the conflicting requirements of standardized tests and the need to cultivate 21st-century skills, deeper learning, and transferable knowledge, among others. This paper presents a pilot implementation that could address both problems. Selected teachers attended an NSF-funded Research Experience for Teachers (RET) summer program to learn about chip design basics. They also received curriculum development support to design new modules on semiconductor topics that would attract their students' interests. 

With the passage of the Chips and Science Act, semiconductor workforce development has become front and center for US universities. Among the many skills needed for undergraduates to enter the semiconductor industry, debugging is an important skill that is rarely taught. As the transistor count and complexity of today’s chips grow, thanks to Moore’s Law, fewer new chips can work perfectly for the first time. Hence, much engineering effort is put into debugging, a process that identifies and fixes any discrepancies between the expected and measured chip behavior. This paper first investigates the need and the economic incentives of debugging in the semiconductor industry. It was estimated that a typical semiconductor project spent 35 to 50 percent of its time in debugging. The need for silicon debugging has led to a new profession called validation engineers. Debugging has also gained the nickname of the Schedule Killer, highlighting its impact on the project schedule and the company’s bottom line. Next, the paper summarizes existing cognitive models of troubleshooting. Early models often failed to capture the role of experience, which was essential for circuit and hardware debugging. Jonassen et al. proposed a troubleshooting learning architecture that includes the contribution of past experiences. This cognitive framework has been successfully applied in computer science and physics education, leading to some of the latest pedagogy innovations, such as collaborative pair debugging. This paper also investigates multiple emotions associated with debugging, such as frustration, fear, and anxiety. These emotions may lead to disengagement and avoidance of the subjects. Debugging may also be related to other non-cognitive factors, such as mindsets. The positive effect of teaching self-theory and a growth mindset has been observed in different age groups. However, studies also found that domain-specific aptitudes were more helpful in changing student’s performance in the subject matter. The takeaway message from this paper is that a genuinely effective debugging education intervention must be holistic and domain-specific. Holistic means that the intervention should address both cognitive and affective components. Domain specificity means that any growth mindset message should be contextually situated within the subject matter materials. How to design such an intervention will be the next million-dollar question, as it not only fills the gap of collegiate debug education in microelectronics but also serves as a critical missing piece toward developing a globally competent semiconductor workforce for generations to come.